Microelectronic circuits for data and/or signal processing contain memories with memory cells which make it possible to store data, state variables etc. The requirements for these memories have become more stringent as processing speed increases. In particular, it has been necessary to shorten considerably both the access time to the contents of the memory (read process) and the time period for writing to the memory (write process). An important example of such memories is the SRAM (Static Random Access Memory) which can be implemented with a small area requirement and allows very rapid access to its content.
An increasing number of portable systems have come on the market recently, such as mobile telephones, palm-top computers and medical equipment (e.g. hearing aids) for example. The voltage supply for these systems is provided by batteries or rechargeable batteries. The operating time and standby time of portable equipment in this case depends on the one hand on the battery capacity and on the other hand on the power consumption of the system components. In the case of microelectronic circuits, concepts for reducing the power consumption have already been developed, in order to increase the standby time in this way. See A. P. Chandrakasan, S. Sheng, R. W. Brodersen: "Low-Power CMOS Digital Design", IEEE Journal of Solid-State Circuits, Vol. 27, No. 4, April 1992, pp. 473-484.
The power consumption of microelectronic circuits can essentially be described by the following relationship: ##EQU1## where .sigma..sub.i is the switching frequency of the i-th node, C.sub.i is its capacitance, VDD represents the supply voltage, HUB the level change at a node (HUB=VDD in general in static CMOS logic), and i is a sequential number for all the nodes in the relevant circuit.
The following techniques for power reduction can be derived from Equation (1): lowering the supply voltage, reducing node capacitances and reducing switching frequencies.
In the case of a SRAM memory, circuits have been implemented whose power consumption has already been considerably reduced by means of the techniques mentioned above: lowering the supply voltage from 5 volts to 3.3 volts (in some cases 2.4 V), precharging the bit lines to VDD/2 instead of VDD (level reduction), minimizing the capacitance by means of a compact layout (that is to say small number of transistors and small wiring capacitances), and by dividing the memory into blocks which can thus be driven individually (that is to say reduced switching frequency).
A 6-transistor memory cell is known from D. Rhein, H. Freitag: "Mikroelektronische Speicher", Springer Press 1992, pp 50-51, 56-57, and is also illustrated in FIG. 2. The memory cell SZ comprises two inverters MN5, MP3 and MN6, MP4 with feedback. The output node A of the inverter MN5, MP3 is connected to a first bit line BL via a first selection transistor MN1 which is driven via a word line WL. The output node B of the inverter MN6, MP4 is connected to a second bit line BLQ via a second selection transistor MN2 which is likewise driven by the word line WL. The corresponding transistors in the two inverters have the same dimensions, that is to say MP3=MP4 and MN5=MN6.
An important feature of a SRAM, designed with the described 6-transistor memory cell (FIG. 2) and differentially operating read amplifiers (see Rhein, supra), is the fact that the bit lines are driven in pairs. During writing, mutually complementary levels (for example BL=1 and BLQ=0) are applied to BL and BLQ corresponding to the datum and only then can the inverter pair (comprising MN5, MN6, MP3 and MP4) with feedback be switched over (A from 0 to 1; B from 1 to 0) via the selection transistors MN1 and MN2, which are switched on by WL. At the start of a reading process, both nodes BL and BLQ are at the same potential in order that they can then be drawn to mutually complementary levels by a driven memory cell (MN1 and MN2 are switched on by WL). A differentially operating read amplifier then allows rapid assessment of the difference between BL and BLQ, and thus reliable reading.
The capacitances of the bit lines BL and BLQ are governed both by the capacitive load of a cell and by the architecture of the memory, and in general they are among the largest capacitances in a SRAM. Since one of the large bit line capacitances must be reversed (.sigma.BL=0.5, .sigma.BLQ=0.5, see Formula (1)) in each case both during the reading process and during the writing process depending on the driven memory cell, a large proportion of the power consumption of a SRAM is caused at this point.
Any reduction in the switching frequency of bit lines can accordingly lead to a considerable reduction in the SRAM power consumption.
A 6-transistor memory cell is known from IBM Technical Disclosure Bulletin Vol. 31, No. 1 June 1988, page 291, and is also illustrated in FIG. 1. The memory cell SZ comprises a memory element SPE composed of two inverters MN5, MP3 and MN6, MP4 of different dimensions and with feedback. The output node A of the weaker inverter MN5, MP3 is connected to a first bit line BL via a first selection transistor MN1 which is driven via a word line WL. The output node B of the stronger inverter MN6, MP4 is connected to a second bit line BLQ via a second selection transistor MN2 which is driven by a second word line WLS.
In the case of the known circuit, the word line WL is used for writing a bit, and the second word line WLS is used for reading a bit from the memory element SPE using a single-pole read amplifier. VDD and VSS are supply voltages. When reading from this SRAM cell, only the bit line BL experiences a level change, and only the bit line BLQ during writing. It has thus been possible to reduce considerably the switching frequency of the bit lines.
If the supply voltage VDD is lowered to EQU .vertline.Vthmax.vertline.&lt;VDD&lt;.vertline.Vthp.vertline.+.vertline.Vthn.vert line. (2)
(Vthp, Vthn: threshold voltage of the N(P)-channel transistors, Vthmax being the greater value of Vthp and Vthn) in order to reduce the power consumption, the operation of the memory cell according to IBM, supra, (FIG. 1) is not ensured. When writing a 1 (BL=VDD), the charge on the node A is changed only to V=VDD-Vthn, since a voltage drop .DELTA.V of .DELTA.V=Vthn occurs across the selection transistor MN1. The inverter comprising MP4 and MN6 cannot switch over with this voltage level at the node A, and storage therefore does not take place. It is not possible to use the memory cell according to IBM, supra, (FIG. 1) in the voltage range according to Rhein, supra.